The development of complicated integrated circuits often requires powerful numerical simulation programs. For example, circuit simulation is an essential part in the design flow of integrated circuits, helping circuit designers to verify the functionality and performance of their designs without going through expensive fabrication processes. Examples of electronic circuit simulators include the Simulation Program with Integrated Circuit Emphasis (SPICE) developed at the University of California, Berkeley (UC Berkeley), and various enhanced versions or derivatives of SPICE, such as SPECTRE, developed by Cadence Design Systems, Inc. SPICE and its derivatives or enhanced versions will be referred to hereafter as SPICE circuit simulators, or SPICE.
An integrated circuit is a network of circuit elements such as resistors, capacitors, inductors, mutual inductors, transmission lines, diodes, bipolar junction transistors (BJT), junction field effect transistors (JFET), metal-oxide-semiconductor field effect transistors (MOSFET), metal-semiconductor field effect transistors (MESFET), thin-film transistors (TFT), etc. SPICE models a circuit in a node/element fashion, i.e., the circuit is regarded as a collection of various circuit elements connected at nodes. At the heart of SPICE is the so-called Nodal Analysis, which is accomplished by formulating nodal equations (or circuit equations) in matrix format to represent the circuit and by solving these nodal equations. The circuit elements are modeled by device models, which produce model results that are represented in the circuit equations as matrices.
A device model for modeling a circuit element, such as the SPICE model for modeling MOSFET devices, developed by UC Berkeley, typically includes model equations and a set of model parameters that mathematically represent characteristics of the circuit element under various bias conditions. For example, a circuit element with n terminals can be modeled by the following current-voltage relations:Ii=fi(V1, . . . , Vn, t) for i=1, . . . , n,where Ii represents the current entering terminal I; Vj(j=1, . . . , n) represents the voltage or terminal bias across terminal j and a reference terminal, such as the ground; and t represents the time. The Kirchhoff's Current Law implies that the current entering terminal n is given by
      I    n    =            ∑              i        =        1                    n        -        1              ⁢                  ⁢                  I        i            .      A conductance matrix of the circuit element is defined by:
  G  ⁢          ⁢                              (                      V                          1              ,                                                            …          ⁢                                          ,                                                  V            n                    ,                                                  t            )                    :=                                    (                                                                                                                  ∂                                                  f                          1                                                                                            ∂                                                  V                          1                                                                                                                          ⋯                                                                                                      ∂                                                  f                          1                                                                                            ∂                                                  V                          n                                                                                                                                                          ⋮                                                        ⋰                                                        ⋮                                                                                                                                      ∂                                                  f                          n                                                                                            ∂                                                  V                          1                                                                                                                          ⋯                                                                                                      ∂                                                  f                          n                                                                                            ∂                                                  V                          n                                                                                                                                )                        .                              To model the circuit element under alternating current (AC) operations, the device model also considers the relationship between node charges and the terminal biases:Qi=qi(V1, . . . , Vn, t) for i=1, . . . , n.where Qi represents the node charge at terminal i. Thus, the capacitance matrix of the n-terminal circuit element is defined by
  C  ⁢          ⁢                              (                      V                          1              ,                                                            …          ⁢                                          ,                                                  V            n                    ,                                                  t            )                    :=                                    (                                                                                                                  ∂                                                  q                          1                                                                                            ∂                                                  V                          1                                                                                                                          ⋯                                                                                                      ∂                                                  q                          1                                                                                            ∂                                                  V                          n                                                                                                                                                          ⋮                                                        ⋰                                                        ⋮                                                                                                                                      ∂                                                  q                          n                                                                                            ∂                                                  V                          1                                                                                                                          ⋯                                                                                                      ∂                                                  q                          n                                                                                            ∂                                                  V                          n                                                                                                                                )                        .                              
A complex integrated circuit may contain millions of circuit elements such as transistors, resistors, and capacitors. The design and simulation of such a complex integrated circuit may involve multiple teams of engineers. It is advantageous to partition the design of such complex integrated circuit using a hierarchical approach, whereby certain circuit elements are grouped together and may be reused repeatedly through the integrated circuit or in a subsequent design. A method and system for design and simulation of an integrated circuit with a hierarchical data structure are disclosed by U.S. patent application Ser. No. 10/724,277, entitled “System and Method for Simulating a Circuit Having Hierarchical Structure,” which, filed on Nov. 26, 2003 and commonly owned by Cadence Design Systems, Inc., is incorporated expressly by reference in its entirety herein.
Hierarchical simulation is most useful when it can also be applied to simulate a back-annotated flat netlist containing parasitic RC networks. During back-annotation, a flat netlist in DSPF (Detailed Standard Parasitic Format) or SPEF (Standard Parasitic Exchange Format) that consists of millions of RC elements is produced by a process called Parasitic Extraction. The flat netlist is also referred to as a gate-level netlist.
Prior-art circuit simulators simulate a back-annotated circuit as a flat circuit. After reading in the flat netlist, the circuit simulators perform a process known as the RC Reduction on a net by net basis to reduce the number of RC elements within a particular RC network in the flat netlist. Various techniques for performing RC Reduction are described in “Asymptotic waveform evaluation for timing analysis,” by L. Pillage and R. Rohrer in IEEE Transactions on CAD, vol. 9, no. 4, pp. 352-366, April 1990; “Efficient Linear Circuit Analysis by Pade Approximation via Lanczos Process,” by P. Feldmann and R. Freund in IEEE Transactions on CAD, vol. 14, no. 5, pp. 639-649, May 1995; and “Stable and Efficient Reduction of Large Multiport RC Networks by Pole Analysis via Congruence Transformations,” by K. Kerns and A. Yang in IEEE/ACM DAC, pp. 280-285, 1996.
However, after the RC Reduction process, the prior-art circuit simulators simulate the design using the flat netlist. As a result, the performance of the simulation suffers significantly because of the large number of circuit elements, such as the back-annotated parasitic resistors and capacitors that have to be simulated. Additionally, simulating the flat netlist requires more memory because of the large number of circuit elements of the back-annotated flat netlist.
Therefore, methods and systems for determining electrical isomorphism between two electrical networks are needed for improving the efficiency of simulating an integrated circuit with its parasitic RC networks after back-annotation.